(1) Field of the Invention
The invention generally relates to integrated circuit devices, more specially devices each with a stacked capacitor overlaying the regions of transistor electrode, trench, and field oxide, and still more specially to a process for producing a charge storage capacitor for a DRAM (dynamic random access memory) that has a large capacity and occupies less space on the device.
(2) Description of the Prior Art
In recent years there has been a dramatic increase in the packing density of DRAMs. Large DRAM devices are normally silicon based, and each cell typically embodies a single MOS field effect transistor with its source connected to a storage capacitor. This large integration of DRAMs has been accomplished by a reduction in individual cell size. However, a decrease in storage capacitance, which results from the reduction in cell size, leads to draw backs, such as a lowering s/d ratio and undesirable signal problems in terms of reliability. In order to achieve the desired higher level of integration, it requires the technology to keep almost the same storage capacitance on a greatly reduced cell area.
Efforts to maintain or increase the storage capacitance in memory cells with greater packing densities are evident in U.S. Pat. No. 4,742,018, which discloses a stacked capacitor. The publication "Stacked Capacitor Cells for High-Density Dynamic RAMs" by Watanabe et al, page 600, IEDM, 1988, shows a stacked capacitor and a process for making it that is suited for use in 16 Megabit dynamic RAMs. Another approach to achieve sufficient capacitance in high density memories is the use of a stacked trench capacitor cell, as disclosed in "Process Technologies for High Density High Speed 16 Megabit Dynamic RAMs" by Horiguchi et all, page 324, IEDM, 1987.
It is well known that in the art of integrated circuit device manufacture, one of the primary goals is increasing the number of device that can be placed into a given unit space on the semiconductor chip. As the traditional fabrication process begin to approach the limit of reduction, considerable attention has been applied to forming device elements on over and above the wafer to take advantage of extra versatility of third dimension.
One of the successful vertically oriented integrated circuit devices is the stacked capacitor. Briefly, a stacked capacitor is formed by forming the stacked capacitor structures laying over the gate electrode on active and field oxide regions and diffusion region.
One such stacked capacitor for a dynamic random access memory (DRAM) cell has two transistors with word lines and as the gates of transistors. The memory bit line connects to one of the source/drain regions and the other source/drain region of the transistor is tied to one plate of the capacitor. The capacitor is formed by polysilicon plate, stacked dielectric and polysilicon node laying over the transistor gates and one of the diffusion region of the transistor. The capacitor is extended to cover the work line in order to increase the capacitance of the stacked cell. The limitation of the stacked capacitor is that the polysilicon plate and polysilicon node can not extend too much over the field region due to the limitation of patterning resolution, typically, about 0.5 micrometers.
In order to increase the capacitance of stacked capacitor within the limited chip area, the step height of capacitor over transistor gate is increased by additional deposition and patterning of polysilicon as shown in FIG. 3, disclosed by Hidenhire Watanabe et al, p 600 to 603, IEDM 1988.
Not withstanding, the aforedescribed capacitor structure, there is a need for even greater capacitance for a given space in order to achieve even greater packing densities, and improve the field of DRAMs and other device.